Digital signal processors (DSPs) include an accumulator for temporarily storing data generated by the one or more data processing units in the DSP. Commonly, the accumulator comprises multiple storage locations for simultaneously storing multiple, separate, pieces of data. Such an accumulator might be comprised of a register file. Sometimes each separate storage location in a processor core is termed an accumulator and thus, under this terminology, the processing core comprises many separate accumulators. In this specification, all temporary storage locations in a processor core are collectively termed an accumulator and each individually accessible storage location is termed an accumulator register.
The data processing units in the DSP, for example, may comprise one or more of each of an arithmetic logic unit (ALU), a bit manipulation unit (BMU), a multiply and accumulate unit (MAC), an adder, etc. Instructions in the instruction set of a DSP commonly call for the value generated at the output of one or more of the data processing units to be stored to one of the registers in the accumulator. Another instruction may call for data stored in one or more of the accumulator registers to be read out to the input of one or more of the data processing units to be used in the generation of further data by the data processing unit. Even further, instructions may call for data stored in one or more accumulator registers to be read out to memory via a data bus. A single instruction may even include a combination of two or more of any of the aforementioned operations. In order for the use of multiple data processing units in a DSP to be efficient, the accumulator must have multiple read ports and multiple write ports so that the multiple pieces of data needed to execute an instruction and/or the multiple pieces of data generated as a result of the execution of an instruction can all be written to and/or read from the accumulator during the execution of the instruction.
From a chip area perspective, read and write ports for an accumulator consume large amounts of chip area. Accordingly, an increase in the number of accumulator read and/or write ports in a DSP significantly increases the required size of the DSP data path. Further, as the number of read or write ports of an accumulator increases, the access time for the accumulator also increases. Thus, as the number of accumulator read and write ports increases, a slower and slower clock speed must be used, since the read access time will be in a timing critical path in virtually all practical DSPs.
Depending on the complexity of the DSP and the instruction set, a single instruction may call for the writing of multiple pieces of data to different registers in the accumulator as well as the reading out of the data from multiple registers in the accumulator to different destinations, such as an input of one of the data processing unit or memory.
Accordingly, it is an object of the present invention to reduce the number of read ports of an accumulator in a processor without any loss in functionality.
It is another object of the present invention to provide an improved digital signal processor.
It is another object of the present invention to provide a faster digital signal processor.
It is a further object of the present invention to provide a smaller digital signal processor without loss in functionality.
It is yet another object of the present invention to provide a less expensive digital signal processor without loss in functionality.